
By Stephan Henzler
With ongoing expertise scaling excessive answer within the voltage area turns into more and more complicated. Time area solution, notwithstanding, is always bettering as electronic circuits turn into quicker in every one new expertise iteration. Time-to-Digital Converters describes the basics of time-to-digital converters (TDC) according to analog and electronic conversion rules. a detailed theoretical research is supplied with appreciate to quantization, linearity, noise, and variability. complex TDC architectures are defined that tackle the demanding situations of signed time period size, lengthy size time, excessive solution, excessive linearity, low-power, variability and calibration, low mismatch between a number of measurements, and suitability for layout automation. answer enhancement innovations corresponding to pulse-shrinking, Vernier delay-line, neighborhood passive interpolation, gated delay-lines, and time amplification are brought and mentioned with admire to working precept, solution, energy, zone, conversion time, susceptibility to adaptations, and suitability for implementation and mass creation. eventually, an outline on TDC functions in phase-locked-loops and analog-to-digital converters is given. Time-to-Digital Converters provides a powerful theoretical foundation and includes a different intensive review on TDC architectures and conversion rules.
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Example text
6 Noise Shaping in Time-to-Digital Converters 33 Ti mi−1 εi−1 mi εi ti−1 N’i−1 Ni Ni−1 N’i ti Fig. 41) shows that both the quantization noise as well as the physical noise are first order noise shaped. e. correlated noise. If the noise component mi is given by mi−1 plus another noise component the latter one is directly visible at the output without noise shaping. 42) These noise errors accumulate along the delay-line statistically. 44) 34 3 Theory of TDC Operation This means that all noise that is picked up between the time instances spanning the measurement interval directly contributes to the measurement uncertainty.
4) where a short delay-line is bent into a loop and traversed several times by the start event. As the start signal is fed into the delay-line again, when it has reached its end, the expression “reference recycling” is sometimes used to describe looped TDCs. A counter determines how often the delay-line has been passed by the start event before the TDC is stopped. e. the fine resolution BT DC . 1) B = M · Bcnt + BT DC where M is the number of delay elements within the delay-line. 46 4 Advanced TDC Design Issues stop start loop counter Fig.
The calculation with individual stop signals is done accordingly. Chapter 4 Advanced TDC Design Issues Abstract In this chapter architectural aspects of time-to-digital converters are discussed in detail. The design challenges are a high dynamic range, small offset and gain error, high linearity, a small die area, and finally a low power consumption. The time resolution is independently addressed in Chapter 5. Several architectures are proposed that particularly focus on at least one of the design challenges.